Architecture
AMBA AHB bus-based for high-speed devices
AMBA APB bus-based for low-power devices
Embedded Processor Faraday FA626TE
ARM based 32-bit RISC
Up to 533 MHz
32-kB instruction cache and 32-kB data cache
High speed I/O Interface USB 2.0 OTG
USB 2.0 HOST
SATAII X2 (3 Gbps)
GMII/MII/RMII
Capture Interface ITU BT-656 input x4 (Up to 108 MHz)
3D-deinterlace
Cacade input x1 (Up to 108 MHz)
Display Interface
Analog VGA output (150 MHz DAC)
NTSC/PAL composite output
ITU bt.1120 digital output (74.25 MHz)
Memory Interface
16-bit DDR2 SDRAM interface x 2
8-bit Shared asynchronous SRAM/ROM/flash interface
DMA controller
USB 2.0 OTG controller
USB 2.0 Host controller
SATA Host controller
Video capture (NTSC/PAL)
Display controller (Max. 1080i)
H.264 codec
JPEG codec
AES/DES/3DES cipher controller
10/100/1000 Ethernet MAC controller
PCI bridge
SDIO/SDHC
APB Bus Components
Timer
Watch dog timer
Real time clock
Interrupt controller
GPIO x4
I2C
I2S x3
Full-function UART x 1 + Console UART x 1 (Or Console UART x 5)
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H.264 Codec
Supports the baseline profile encoding up to D1 at 120 fps (Max.)
Supports the baseline profile decoding up to D1 at 60 fps (Max.)
JPEG Codec Up to D1 at 60 fps
Video Capture Interface Supports four BT.656 input ports at 108 MHz
The max. resolution is 720x480 (NTSC) or 720x576 (PAL)
Supports 54 MHz/108 MHz pixel/frame interleave mode
Flexible design for video decoder and multiplexer interface
Supports size down
Supports eight private region masks in each channel
Supports font-based OSD in recording channel
Provides clock output to video decoder to save external oscillator (27 MHz, 54 MHz, 108 MHz)
Display Controller
Supports 1080/60i, 720/60p, 480/60i, 576/60i resolution
Integrate 27 MHz DAC for composite output (NTSC/PAL)
Integrate 150 MHz DAC for VGA output
Supports font-based OSD for display outputs
Supports three graphic planes and hardware cursor
Embedded Analog Device
USB 2.0 OTG PHY
USB 2.0 HOST PHY
SATA2.0 PHY
Clock/PLL 12 MHz and 12.288 MHz (Optional) oscillators
Programmable frequency PLL
Programmable clock output x2 (25/27/54/108 MHz)
Power Management
Clock gating control for individual components
Normal operation
Operating Frequency
CPU/DDR/AHB: 533/356/178 MHz or 480/480/240 MHz
Operating Voltage
1.2 V for core
3.3 V for input/output with 5-V tolerance
1.8 V for DDR DRAM I/O
Process UMC 0.13 µm logic process
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